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CSE Dissertation Defense: Liang Zhou

Aug 3
1 p.m.
3 p.m.
Jolley Hall, Room 309

​"Self-powered Time-Keeping and Time-of-Occurrence Sensing"

Liang Zhou
Adviser: Shantanu Chakrabartty

Self-powered and passive Internet-of-Things (IoT) devices (e.g. RFID tags, financial assets, wireless sensors and surface-mount devices) have been widely deployed in our everyday and industrial applications. While diverse functionalities have been implemented in passive systems, the lack of a reference clock limits the design space of such devices used for applications such as time-stamping sensing, recording and dynamic authentication. Self-powered time-keeping in passive systems has been challenging because they do not have access to continuous power sources. While energy transducers can harvest power from ambient environment, the intermittent power cannot support continuous operation for reference clocks. The thesis of this dissertation is to explore and implement self-powered time-keeping devices on standard CMOS processes.  

In this dissertation, a novel device that combines the physics of quantum tunneling and floating-gate (FG) structures is proposed for self-powered time-keeping in CMOS process. The proposed device is based on thermally assisted Fowler-Nordheim (FN) tunneling process across high-quality oxide layer to discharge the floating-gate node, therefore resulting in a time-dependent FG potential. The device was fully characterized in this dissertation, and it does not require external powering during runtime, making it feasible for passive devices and systems. Dynamic authentication protocols were explored and proposed based on the dynamic signatures generated by the FN timers, and they were proven to be secure and lightweight enough for passive devices that have limited computational and storage resources. We further explored the modalities that can sense the time-of-occurrence of events. Prototyped SoCs were designed and deployed to sense and record the time-of-occurrence of mechanical events. All the designs were prototyped and fabricated on a standard 0.5-m CMOS process, and the measurements were conducted to validate the designs.