CSE Doctoral Student Seminar: Clayton Faber and Stephen Timcheck

Oct 26, 2018
12:30 p.m.
2 p.m.
Loptata Hall, Room 101

High Level Synthesis Performance Pitfalls in Streaming Applications

Clayton Faber
Adviser: Roger Chamberlain

Streaming applications have been a well suited target for field programmable gate arrays (FPGAs) due to their ability to implement algorithms in hardware. When implemented in hardware a streaming application can take advantage of custom data flow paths between computational nodes. The task of implementing computational work in FPGAs for heterogeneous systems is now easier thanks to the proliferation of various high level synthesis (HLS) tools. However, there are still gaps in HLS tool-chains that result in sub-optimal results compared to hand tooled implementations. In this work, OpenCL is used to implement data integration applications and target an FPGA node. In this presentation there will be an exploration into the impact that certain optimizations, implementations, and computational styles have on the data integration applications.

Precise Signaling for Streaming Applications in MERCATOR

Stephen Timcheck
Adviser: Jeremy Buhler

With the advancement of parallel processing technologies, it has become increasingly important to develop methods for implementing highly parallelizable irregular data streaming applications. In particular, we wish to introduce precise control signaling into SIMD-parallel streaming frameworks for greater application breadth. That is, we wish to explore methods to precisely order the processing of control directives with respect to the data stream through the use of a signaling protocol. This problem is particularly interesting due to the inherent sequential properties of control handling. Of these types of frameworks, we specifically target MERCATOR, a SIMD-parallel streaming framework developed by our lab, which is used to implement parallel data streaming applications on the GPU through CUDA.